1. Field of the Invention
The invention relates to a calibration technique for a gated oscillator, and more particularly to a background calibration technique for a gated oscillator.
2. Description of the Related Art
Because gated oscillators can perform instantaneous phase realignment to input signals, they have recently grown in demand. Applications of gated oscillators include Burst Mode Clock and Data Recovery (BMCDR), low noise clock generation . . . etc. A burst mode CDR circuit is a circuit or circuit element that synchronizes or recovers timing information from a burst of formatted data applied to or input to the CDR circuit. However, one drawback of the gated oscillators is that the inherent frequency offset between the gated oscillators and input signals results in BER degradation or unwanted spurs. Conventionally, a Phase Locked Loop (PLL) with a replica gated oscillator can be used to track on-chip Process, Voltage and Temperature (PVT) variations. However, the approach requires additional circuit area for the replica, and a mismatch between the gated oscillator and the replica unavoidably occurs.
In another conventional approach, a local reference frequency is included to calibrate the frequency offset between the gated oscillators and input signals. However, the mismatch between the local reference clock and the input data rate still exits, which means a high-precision local clock source that would greatly increase the circuit cost is required. Therefore, an efficient background calibration technique is highly required.